1. Field of the Invention:
This invention relates to a method and a device for interfacing an image scanner with an image processing device. More particularly, this invention relates to a method for speedily transferring video signals, which are obtained as a result of scanning a given objective image with a portable image scanner, to an image processing device such as a computer and a word processor, and to an interface circuit used for practicing this method.
2. Description of the Prior Art
In image processing systems, an interface is required for linking an image reading device such as an image scanner and an image processing device such as a computer and a word processor. A desktop image scanner capable of automatically scanning a given objective image at a constant speed can easily effect synchronous transfer of video data signals obtained as a result of scanning to the image processing device. On the other hand, a portable image scanner, which is manually moved in a sub-scanning direction in order to read the objective image, is very difficult to control the timing of the video data transfer to the image processing device. The interface for use in such a manual image scanner necessitates not only a function of transferring electrical signals from the image scanner to the image processing device, but also a function of temporarily storing the video signals in a memory and outputting the stored video signals by prescribed bits thereof each time the image scanner is manually moved for one sub-scanning line on the objective image.
The timing of video data transfer from the image scanner to the interface has heretofore been controlled by use of synchronous clock pulses generated by an external host computer for image processing in a conventional image processing system.
Japanese Patent Application Public Disclosure No. SHO 63-33058(A) discloses an interface circuit by which video data having some bits of high order which indicate the sub-scanning line being read are temporarily stored and transferred to a host computer while being timed under the control of the host computer, as illustrated schematically in FIG. 1. This image reading device in the prior art system adopts a portable image scanner I/S composed of an image sensor 1 such as a CCD device for optically reading out a given objective image I, a digitizer 2 for digitizing analog image signals outputted from the image sensor 1 to the corresponding binary-coded video signals Vs, a sub-scanning encoder 3 which generates sub-scanning clock pulses Ep in accordance with rotation of a roller for allowing the image scanner I/S to move in a sub-scanning direction, and a timing pulse generator 4 for generating address-up signals Ta and addressing signals Tb by dividing standard timing clock pulses. The interface circuit I/F in the prior art system is composed of a shift register 5 for storing the video signals Vs outputted in sequence from the image scanner I/S, a counter 6 for counting the address-up signals Ta and the addressing signals Tb, a switching circuit (Sw.) 7 consisting of flip-flop circuits and adapted to permit the video signals Vs stored in the shift register 5 to be transferred to the external image processing device (host computer) H/C upon reception of a transfer permission signal given by the aforesaid counter 6, and a memory 8 for storing all the video signals Vs which are fed from the shift register 5 via the switching circuit 7 while being addressed by the counter 6. The memory 8 is allowed to transfer the video signals stored therein to the external host computer H/C upon reception of a transfer command So from the host computer H/C. To be more specific, the video signals fed in serial from the image scanner I/S are temporarily stored in the shift register 5, and thereafter, transferred by one unit of n-bits (e.g. n=8) in parallel to the memory 8 by the permission of the switching circuit 7. Though the video signals Vs are stored in the memory 8 while being addressed by an addressing counter 6a in the counter 6, the transferring of the video signals Vs by one transfer unit of n-bits to the memory 8 is managed by an address-up counter 6b in the counter 6. Upon completion of reading all picture elements (e.g. 1024 pixels) for one sub-scanning line, a sub-scanning pulse Ep, which is generated by the sub-scanning encoder 3 each time the sub-scanning line is updated, is given to the host computer H/C through the interface I/F, and a sub-scanning condition is validated by the host computer before the transfer command So with addressing data is sent from the host computer H/C to both the counter 6 and memory 8. When the transfer command So is given to input-stage gates of the counters 6a, 6b, these counters are reset to assume their inactive state. In this state, the video signals for one sub-scanning line are transferred to the host computer H/C.
The aforementioned interface circuit in the prior art image processing system calls for large capacity memories capable of storing a mass of video data representing the informations of all the picture elements (e.g. 1024 pixels) in one sub-scanning line together with addressing data specifying the address of every pixel in the memory. This entails a disadvantage that adoption of the large capacity memory adds to the size and complexity of the interface and renders the image processing system scanning condition by the external host computer upon reception of the encoder pulse generated every updating of sub-scanning operation in the image scanner, before the video data stored in the shift register are transferred to the host computer through the switching circuit. However, the video signals outputted in sequence from the image scanner are inhibited from being written in the shift register when one sub-scanning is completed to reset the counter. Thus, in the course of transferring the video data stored in the shift register to the external host computer, image reading operation is interrupted. In other words, in order to continue the image reading operation which is effected by manually moving the portable image scanner in the sub-scanning direction, the image scanner should be moved as slow as possible. Fast movement of the image scanner will cause a sub-scanning error.
From the foregoing, it can be seen that the prior art system including the aforementioned conventional interface circuit has been subject to the control of an external control system such as the host computer and could not conduct concurrently the image reading-out processing and the data transferring processing. Thus, the conventional interfaces prevent the realization of a high-speed image processing system excellent in performance.